Digital System Design
| Rakennetyyppi: | Opintojakso |
|---|---|
| Koodi: | IITS2102 |
| Tyyppi: | Pakollinen valinnainen (vaihtoehtoinen) / Ammattiopinnot |
| OPS: | IT 2015 |
| Taso: | Insinööri (AMK) |
| Opiskeluvuosi: | 3 (2017-2018) |
| Laajuus: | 4 op |
| Vastuuopettaja: | Liu, Yang |
| Opetuskieli: | Englanti |
Toteutukset lukuvuonna 2017-2018
| Tot. | Ryhmä(t) | Opiskeluaika | Opettaja(t) | Kieli | Ilmoittautuminen |
|---|---|---|---|---|---|
| 7 | I-IT-3N | 1.9.2017 – 22.12.2017 | Santiago Chavez Vega | Englanti | 23.8.2017 – 18.9.2017 |
Osaamistavoitteet
This course descibes the necessary steps to design digital system in an efficient way. The course aims to illustrate the importance of structured design methods and ways of working. It shows how to design complex system using simple tasks. Introdcution to design tools is given at the end of the course.
Opiskelijan työmäärä
Total work load of the course: 108 h
- of which scheduled studies: 56 h
- of which autonomous studies: 52 h
Edeltävät opinnot / Suositellut valinnaiset opinnot
Digital Electronics I, Digital Electronics II.
Sisältö
Multilevel Logic. Variable Entered Mapping. Multi-output Minimization. Timing and Timing diagrams. Race and Hazard. Look-Up Tables (LUTs). State Machines. State Diagram. Mealy and Moore. State Encoding. State Minimization. Asynchronous Sequential nets. Timing for Sequential nets. Common Digital Circuits. Devices: ASIC, CPLD, FPGA. How to select a device for a specific application. Tools. Design Flow. Synthesis Tools. Verification Tools.
Opiskelumateriaali
Lecture notes.
Opetusmuoto / Opetusmenetelmät
Lectures, tutorials.
Arviointikriteerit
1: Can analyze timing diagram and build state machines.
3: Can analyze timing diagram, build state machines, encode state machines into minimized form of boolean expressions.
5: Can design complete digital system using standard design flow.
Arviointimenetelmät
Exercises 30 % and an examination 70 %.