Digital System Design

Structure Type:	Study unit
Code:	IITS2102
Type:	Optional obligatory / Professional Studies
Curriculum:	IT 2015
Level:	Bachelor of Engineering
Year of Study:	3 (2017-2018)
Credits:	4 cr
Responsible Teacher:	Liu, Yang
Language of Instruction:	English

Courses During the Academic Year 2017-2018

Impl.	Group(s)	Study Time	Teacher(s)	Language	Enrolment
7	I-IT-3N	2017-09-01 – 2017-12-22	Santiago Chavez Vega	English	2017-08-23 – 2017-09-18

Learning Outcomes

This course descibes the necessary steps to design digital system in an efficient way. The course aims to illustrate the importance of structured design methods and ways of working. It shows how to design complex system using simple tasks. Introdcution to design tools is given at the end of the course.

Student's Workload

Total work load of the course: 108 h
- of which scheduled studies: 56 h
- of which autonomous studies: 52 h

Prerequisites / Recommended Optional Courses

Digital Electronics I, Digital Electronics II.

Multilevel Logic. Variable Entered Mapping. Multi-output Minimization. Timing and Timing diagrams. Race and Hazard. Look-Up Tables (LUTs). State Machines. State Diagram. Mealy and Moore. State Encoding. State Minimization. Asynchronous Sequential nets. Timing for Sequential nets. Common Digital Circuits. Devices: ASIC, CPLD, FPGA. How to select a device for a specific application. Tools. Design Flow. Synthesis Tools. Verification Tools.

Mode of Delivery / Planned Learning Activities and Teaching Methods

Lectures, tutorials.

Assessment Criteria

1: Can analyze timing diagram and build state machines.
3: Can analyze timing diagram, build state machines, encode state machines into minimized form of boolean expressions.
5: Can design complete digital system using standard design flow.

Assessment Methods

Exercises 30 % and an examination 70 %.

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