Digital System Design
| Structure Type: | Study unit |
|---|---|
| Code: | IITS2102 |
| Type: | Optional obligatory / Professional Studies |
| Curriculum: | I-IT 2010 |
| Level: | Bachelor of Engineering |
| Year of Study: | 3 (2012-2013) |
| Credits: | 4 cr |
| Responsible Teacher: | Liu, Yang |
| Language of Instruction: | English |
Courses During the Academic Year 2012-2013
| Impl. | Group(s) | Study Time | Teacher(s) | Language | Enrolment |
|---|---|---|---|---|---|
| 1 | I-IT-3N | 2013-01-07 – 2013-04-26 | Yang Liu | English | 2012-12-07 – 2013-03-04 |
Learning Outcomes
This course descibes the necessary steps to design digital system in an efficient way. The course aims to illustrate the importance of structured design methods and ways of working. It shows how to design complex system using simple tasks. Introdcution to design tools is given at the end of the course.
Student's Workload
Total work load of the course: 108 h
- of which scheduled studies: 56 h
- of which autonomous studies: 52 h
Prerequisites / Recommended Optional Courses
Digital Electronics I, Digital Electronics II.
Contents
Multilevel Logic. Variable Entered Mapping. Multi-output Minimization. Timing and Timing diagrams. Race and Hazard. Look-Up Tables (LUTs). State Machines. State Diagram. Mealy and Moore. State Encoding. State Minimization. Asynchronous Sequential nets. Timing for Sequential nets. Common Digital Circuits. Devices: ASIC, CPLD, FPGA. How to select a device for a specific application. Tools. Design Flow. Synthesis Tools. Verification Tools.
Recommended or Required Reading and Other Learning Resources/Tools
Lecture notes.
Mode of Delivery / Planned Learning Activities and Teaching Methods
Lectures, tutorials.
Assessment Criteria
1: Can analyze timing diagram and build state machines.
3: Can analyze timing diagram, build state machines, encode state machines into minimized form of boolean expressions.
5: Can design complete digital system using standard design flow.
Assessment Methods
Exercises 30 % and an examination 70 %.